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| CY2303 Phase-Aligned Clock Multiplier Features * 3-multiplier configuration (1x, 2x, 4x Ref) * 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) * Phase Alignment * 80 ps typical period jitter * Output enable pin * 3.3V operation * 5V Tolerant input * 8-pin 150-mil SOIC package * Commercial and Industrial Temperature available Functional Description The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows user to obtain 1x, 2x, and 4x Ref output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2303 is available in commercial and industrial temperature ranges. Selector Guide Part Number CY2303SC, CY2303SXC CY2303SI, CY2303SXI Outputs 3 3 Input Frequency Range 10 MHz-41.67 MHz 10 MHz-41.67 MHz Output Frequency Range 10 MHz-166.67 MHz 10 MHz-166.67 MHz Specifics Commercial Temperature Industrial Temperature Block Diagram FBK Pin Configuration 8-pin SOIC Top View x1 REF REFIN PLL x2 REFx2 REF GND REFIN N/C 1 2 3 4 8 7 6 5 OE VDD REFx4 REFx2 x4 OE REFx4 Cypress Semiconductor Corporation Document #: 38-07249 Rev. *B * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised August 2, 2005 CY2303 Pin Description Pin 1 2 3 4 5 6 7 8 REF GND REFIN N/C REFx2 REFx4 VDD OE Signal[1] REF output (1x Reference input) Ground Input reference frequency, 5V tolerant input No Connect 2x Reference input 4x Reference input 3.3V Supply Output Enable (weak pull-up) Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Description Maximum Ratings Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage (Except Ref)...............-0.5V to VDD + 0.5V DC Input Voltage REFIN ........................................-0.5 to 7V Operating Conditions for CY2303SC Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance, 133.33 MHz < Fout < 166.67 MHz Input Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 0 - - - 0.05 Max. 3.6 70 18 12 7 50 Unit V C pF pF pF ms Electrical Characteristics for CY2303SC Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage[2] Supply Current VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 41.67 MHz Unloaded outputs, REFIN = 25 MHz Unloaded outputs, REFIN = 10 MHz Notes: 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Test Conditions Min. - 2.0 - - - 2.4 - - - Max. 0.8 - 100 50 0.4 - 45 32 18 Unit V V A A V V mA mA mA Document #: 38-07249 Rev. *B Page 2 of 7 CY2303 Switching Characteristics for CY2303SC Commercial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK Rise Time [3] Test Conditions 18-pF load 12-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Min. 10 - 40 - - - - - - - Typ. - - 50 - - - - - 80 - Max. 133.33 166.67 60 1.20 1.20 200 200 400 175 1.0 Unit MHz MHz % ns ns ps ps ps ps ms = t2 / t1 [3] Fall Time[3] Output to Output Skew on rising All outputs equally loaded edges[3] Measured at VDD/2 Delay, REFIN Rising Edge to REF Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the REF pin of the device (pin 1) Measured at Fout < 133.33 MHz, loaded outputs, 18-pF load Stable power supply, valid clocks presented on REFIN Operating Conditions for CY2303SI Industrial Temperature Devices Parameter VDD TA CL tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout <133.33 MHz Load Capacitance, 133.33 MHz < Fout < 166.67 MHz, Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 -40 - - 0.05 Max. 3.6 85 15 10 50 Unit V C pF pF ms Electrical Characteristics for CY2303SI Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage[2] Supply Current VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 41.67 MHz Unloaded outputs, REFIN = 25 MHz Unloaded outputs, REFIN = 10 MHz Note: 3. All parameters are specified with loaded outputs. Test Conditions Min. - 2.0 - - - 2.4 - - - Max. 0.8 - 100 50 0.4 - 48 35 20 Unit V V A A V V mA mA mA Document #: 38-07249 Rev. *B Page 3 of 7 CY2303 Switching Characteristics for CY2303SI Industrial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK Rise Time [3] Test Conditions 15-pF load 10-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Min. 10 - 40 - - - - - - - Typ. - - 50 - - - - - 80 - Max. 133.33 166.67 60 1.20 1.20 200 200 400 175 1.0 Unit MHz MHz % ns ns ps ps ps ps ms = t2 / t1 [3] Fall Time[3] Output to Output Skew on rising All outputs equally loaded edges[3] Measured at VDD/2 Delay, REFIN Rising Edge to REF Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the REF pin of the device (pin 1) Measured at Fout < 133.33 MHz, loaded outputs, 15-pF load Stable power supply, valid clocks presented on REFIN Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 All Outputs Rise/Fall Time 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V OUTPUT Output-Output Skew OUTPUT VDD/2 OUTPUT t5 VDD/2 Document #: 38-07249 Rev. *B Page 4 of 7 CY2303 Switching Waveforms (continued) Input-Output Propagation Delay INPUT VDD/2 FBK t6 VDD/2 Device-Device Skew VDD/2 FBK, Device 1 FBK, Device 2 t7 VDD/2 Test Circuits Test Circuit # 1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Ordering Information Ordering Code CY2303SC CY2303SCT CY2303SI CY2303SIT Lead-free CY2303SXC CY2303SXCT CY2303SXI CY2303SXIT 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel Commercial Commercial Industrial Industrial Package Type 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel Operating Range Commercial Commercial Industrial Industrial Document #: 38-07249 Rev. *B Page 5 of 7 CY2303 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07249 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2303 Document Title: CY2303 Phase-Aligned Clock Multiplier Document Number: 38-07249 REV. ** *A *B ECN NO. 110514 121852 390413 Issue Date 01/07/02 12/14/02 See ECN Orig. of Change SZV RBI RGL Description of Change Change from Spec number: 38-01036 to 38-07249 Power up requirements added to Operating Conditions Information Added Lead-free devices Added typical values for jitter Document #: 38-07249 Rev. *B Page 7 of 7 |
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